The present invention generally relates to semiconductor fabrication methods and devices. More specifically, the present invention relates to techniques to protect low temperature isolation materials that form high aspect ratio elements (e.g., isolation regions) of a semiconductor device.
The advancement in semiconductor integrated circuit technology has facilitated continuous reduction of the physical footprint and dimensions of semiconductor devices formed on semiconductor wafers. As a result, circuit density also continues to increase per chip. For a given chip size, active circuit components, e.g., semiconductor devices, are typically placed in close proximity to each other to maximize circuit density. Electrical isolation regions such as shallow trench isolation (STI) regions are typically formed in the wafer to electrically isolate neighboring semiconductor devices from one another.